LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 725
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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User manual
32.5.10.2 Auto-baud modes
The auto-baud interrupts have to be cleared by setting the corresponding ACR
ABTOIntClr and ABEOIntEn bits.
The fractional baud rate generator must be disabled (DIVADDVAL = 0) during auto-baud.
Also, when auto-baud is used, any write to DLM and DLL registers should be done before
ACR register write. The minimum and the maximum baud rates supported by UART are
function of UART_PCLK, number of data bits, stop bits and parity bits.
When the software is expecting an ”AT" command, it configures the UART with the
expected character format and sets the ACR Start bit. The initial values in the divisor
latches DLM and DLM don‘t care. Because of the ”A" or ”a" ASCII coding (”A" = 0x41,
”a" = 0x61), the UART Rx pin sensed start bit and the LSB of the expected character are
delimited by two falling edges. When the ACR Start bit is set, the auto-baud protocol will
execute the following phases:
1. On ACR Start bit setting, the baud rate measurement counter is reset and the UART
2. A falling edge on UART Rx pin triggers the beginning of the start bit. The rate
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
4. During the receipt of the start bit (and the character LSB for Mode = 0), the rate
5. If Mode = 0, the rate counter will stop on next falling edge of the UART Rx pin. If
6. The rate counter is loaded into DLM/DLL and the baud rate will be switched to normal
ratemin
RSR is reset. The RSR baud rate is switched to the highest rate.
measuring counter will start counting UART_PCLK cycles.
the frequency of the UART input clock, guaranteeing the start bit is stored in the RSR.
counter will continue incrementing with the pre-scaled UART input clock
(UART_PCLK).
Mode = 1, the rate counter will stop on the next rising edge of the UART Rx pin.
operation. After setting the DLM/DLL, the end of auto-baud interrupt IIR ABEOInt will
be set, if enabled. The RSR will now continue receiving the remaining bits of the ”A/a"
character.
=
2 P
------------------------ -
16 2 15
All information provided in this document is subject to legal disclaimers.
CLK
Rev. 00.13 — 20 July 2011
UART baudrate
----------------------------------------------------------------------------------------------------------- -
16
2
+
databits
Chapter 32: LPC18xx USART0_2_3
PCLK
+
paritybits
+
stopbits
UM10430
© NXP B.V. 2011. All rights reserved.
=
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