LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 104

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 78.
Table 79.
<Document ID>
User manual
Name
CLK_M3_SCU_STAT
CLK_M3_CREG_CFG
CLK_M3_CREG_STAT
-
CLK_M3_RITIMER_CFG
CLK_M3_RITIMER_STAT
CLK_M3_USART2_CFG
CLK_M3_USART2_STAT
CLK_M3_USART3_CFG
CLK_M3_USART3_STAT
CLK_M3_TIMER2_CFG
CLK_M3_TIMER2_STAT
CLK_M3_TIMER3_CFG
CLK_M3_TIMER3_STAT
CLK_M3_SSP1_CFG
CLK_M3_SSP1_STAT
CLK_M3_QEI_CFG
CLK_M3_QEI_STAT
-
-
CLK_USB0_CFG
CLK_USB0_STAT
-
CLK_USB1_CFG
CLK_USB1_STAT
-
CLK_VADC_CFG
CLK_VADC_STAT
Name
PM
BASE_STAT
-
CLK_APLL_CFG
Register overview: CCU1 (base address 0x4005 1000)
Register overview: CCU2 (base address 0x4005 2000)
Access
R/W
R
-
R/W
Access
R
R/W
R
-
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R
-
R/W
R
-
R/W
R
All information provided in this document is subject to legal disclaimers.
Address
offset
0x000
0x004
0x008 to
0x0FC
0x100
Rev. 00.13 — 20 July 2011
Address
offset
0x534
0x538
0x53C
0x540 to
0x5FC
0x600
0x604
0x608
0x60C
0x610
0x614
0x618
0x61C
0x620
0x624
0x628
0x62C
0x630
0x634
0x638 to
0x6FC
0x700 to
0x7FC
0x800
0x804
0x808 to
0x8FC
0x900
0x904
0x908 to
0x9FC
0xA00
0xA04
Description
CCU2 power mode register
CCU2 base clocks status register
Reserved
CLK_APLL configuration register
Description
CLK_M3_SCU status register
CLK_M3_CREG configuration register
CLK_M3_CREG status register
Reserved
CLK_M3_RITIMER configuration register
CLK_M3_RITIMER status register
CLK_M3_UART2 configuration register
CLK_M3_UART2 status register
CLK_M3_UART3 configuration register
CLK_M3_UART3 status register
CLK_M3_TIMER2 configuration register
CLK_M3_TIMER2 status register
CLK_M3_TIMER3 configuration register
CLK_M3_TIMER3 status register
CLK_M3_SSP1 configuration register
CLK_M3_SSP1 status register
CLK_M3_QEI configuration register
CLK_M3_QEI status register
Reserved
Reserved
CLK_USB0 configuration register
CLK_USB0 status register
Reserved
CLK_USB1 configuration register
CLK_USB1 status register
Reserved
CLK_VADC configuration register
CLK_VADC status register
Chapter 10: LPC18xx Clock Control Unit (CCU)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 0000
0x0000 0FFF
-
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
Reset value
0x0000 0001
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
-
-
0x0000 0001
-
-
0x0000 0001
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