LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 259

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
15.5.3.5 GPIO port pin registers
15.5.3.6 GPIO masked port pin registers
15.5.3.7 GPIO port set registers
Each GPIO port has one port pin register. Reading these registers returns the current
state of the pins read, regardless of direction, masking, or alternate functions, except that
pins configured as analog I/O always read as 0s. Writing these registers loads the output
bits of the pins written to, regardless of the Mask register.
Table 188. GPIO port pin register (PIN, addresses 0x400F 6100 (PIN0) to 0x400F 611C (PIN7))
Each GPIO port has one masked port pin register. These registers are similar to the
PORT registers, except that the value read is masked by ANDing with the inverted
contents of the corresponding MASK register, and writing to one of these registers only
affects output register bits that are enabled by zeros in the corresponding MASK register.
Table 189. GPIO masked port pin register (MPIN, addresses 0x400F 6180 (MPIN0) to 0x400F
Each GPIO port has one port set register. Output bits can be set by writing ones to these
registers, regardless of MASK registers. Reading from these register returns the port’s
output bits, regardless of pin directions.
Table 190. GPIO port set register (SET, addresses 0x400F 6200 (SET0) to 0x400F 621C
Bit
31:0
Bit
31:0
Bit
31:0
Symbol Description
PORT
Symbol
MPORT
Symbol
SET
bit description
619C (MPIN7)) bit description
(SET7)) bit description
All information provided in this document is subject to legal disclaimers.
Reads pin states or loads output bits (bit 0 = GPIOn[0], bit 1 =
GPIOn[1], ..., bit 31 = GPIOn[31]).
0 = Read: pin is LOW; write: clear output bit.
1 = Read: pin is HIGH; write: set output bit.
Description
Read or set output bits (bit 0 = GPIOn[0], bit 1 =
GPIOn[1], ..., bit 31 = GPIOn[31]).
0 = Read: output bit: write: no operation.
1 = Read: output bit; write: set output bit.
Description
Masked port register (bit 0 = GPIOn[0], bit 1 = GPIOn[1],
..., bit 31 = GPIOn[31]).
0 = Read: pin is LOW and/or the corresponding bit in the
MASK register is 1; write: clear output bit if the
corresponding bit in the MASK register is 0.
1 = Read: pin is HIGH and the corresponding bit in the
MASK register is 0; write: set output bit if the
corresponding bit in the MASK register is 0.
Rev. 00.13 — 20 July 2011
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
Reset
value
ext
Reset
value
ext
259 of 1164
Access
R/W
Access
R/W
Access
R/W