LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 810
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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<Document ID>
User manual
Table 751. Register overview: C_CAN0 (base address 0x400E 2000)
Table 752. Register overview: C_CAN1 (base address 0x400A 4000)
Name
-
IF2_CMDREQ
IF2_CMDMSK
IF2_MSK1
IF2_MSK2
IF2_ARB1
IF2_ARB2
IF2_MCTRL
IF2_DA1
IF2_DA2
IF2_DB1
IF2_DB2
-
TXREQ1
TXREQ2
-
ND1
ND2
-
IR1
IR2
-
MSGV1
MSGV2
-
CLKDIV
Name
CNTL
STAT
EC
BT
INT
TEST
All information provided in this document is subject to legal disclaimers.
RO
RO
R/W
RO
Access
-
RO
RO
-
-
RO
RO
-
RO
RO
-
Access
RO
Rev. 00.13 — 20 July 2011
Address
offset
0x04C -
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC -
0x0FC
0x100
0x104
0x108 -
0x11C
0x120
0x124
0x128 -
0x13C
0x140
0x144
0x148 -
0x15C
0x160
0x164
0x168 -
0x17C
0x180
Address
offset
0x000
0x004
0x008
0x00C
0x010
0x014
Description
Reserved
Message interface 2 command request 0x0001
Message interface 2 command mask
Message interface 2 mask 1
Message interface 2 mask 2
Message interface 2 arbitration 1
Message interface 2 arbitration 2
Message interface 2 message control
Message interface 2 data A1
Message interface 2 data A2
Message interface 2 data B1
Message interface 2 data B2
Transmission request 1
Transmission request 2
Reserved
New data 1
New data 2
Reserved
Interrupt pending 1
Interrupt pending 2
Reserved
Message valid 1
Message valid 2
Reserved
CAN clock divider register
Description
CAN control
Status register
Error counter
Bit timing register
Interrupt register
Test register
Chapter 36: LPC18xx C_CAN
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
-
0x0000
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
0x0000
-
0x0000
0x0000
-
0x0000
0x0000
-
0x0001
Reset
value
0x0001
0x0000
0x0000
0x2301
0x0000
-
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