LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 900

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 827. Register overview: ADC0 (base address 0x400E 3000)
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Table 828. Register overview: ADC1 (base address 0x400E 4000)
Name
INTEN
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
STAT
Name
CR
GDR
-
INTEN
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Access Address
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
Access Address
R/W
R0
-
R/W
All information provided in this document is subject to legal disclaimers.
offset
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
offset
0x000
0x004
0x008
0x00C
Rev. 00.13 — 20 July 2011
A/D Channel 0 Data Register. This register
A/D Channel 1 Data Register. This register
A/D Channel 2 Data Register. This register
A/D Channel 3 Data Register. This register
A/D Channel 4 Data Register. This register
A/D Channel 5 Data Register. This register
A/D Channel 6 Data Register. This register
A/D Channel 7 Data Register. This register
A/D Status Register. This register contains
A/D Control Register. The AD1CR register
A/D Global Data Register. Contains the result
Reserved.
Description
A/D Interrupt Enable Register. This register
contains enable bits that allow the DONE flag
of each A/D channel to be included or
excluded from contributing to the generation
of an A/D interrupt.
contains the result of the most recent
conversion completed on channel 0
contains the result of the most recent
conversion completed on channel 1.
contains the result of the most recent
conversion completed on channel 2.
contains the result of the most recent
conversion completed on channel 3.
contains the result of the most recent
conversion completed on channel 4.
contains the result of the most recent
conversion completed on channel 5.
contains the result of the most recent
conversion completed on channel 6.
contains the result of the most recent
conversion completed on channel 7.
DONE and OVERRUN flags for all of the A/D
channels, as well as the A/D interrupt flag.
Description
must be written to select the operating mode
before A/D conversion can occur.
of the most recent A/D conversion.
A/D Interrupt Enable Register. This register
contains enable bits that allow the DONE flag
of each A/D channel to be included or
excluded from contributing to the generation
of an A/D interrupt.
Chapter 38: LPC18xx 10-bit ADC0/1
UM10430
© NXP B.V. 2011. All rights reserved.
-
Reset
value
0x0000 0100
-
-
-
-
-
-
-
-
0
Reset
value
0x0000 0000
-
0x0000 0100
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