LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 359

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.6.1 Use of registers
Table 300. Register overview: USB0 OTG controller (register base address 0x4000 6000)
The register interface has bit functions described for device mode and bit functions
described for host mode. However, during OTG operations it is necessary to perform
tasks independent of the controller mode.
The only way to transition the controller mode out of host or device mode is by setting the
controller reset bit. Therefore, it is also necessary for the OTG tasks to be performed
independently of a controller reset as well as independently of the controller mode.
Name
BINTERVAL
ENDPTNAK
ENDPTNAKEN
-
PORTSC1_D
PORTSC1_H
-
OTGSC
USBMODE_D
USBMODE_H
Device endpoint registers
ENDPTSETUPSTAT
ENDPTPRIME
ENDPTFLUSH
ENDPTSTAT
ENDPTCOMPLETE
ENDPTCTRL0
ENDPTCTRL1
ENDPTCTRL2
ENDPTCTRL3
ENDPTCTRL4
ENDPTCTRL5
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Access Address
R/W
R/W
R/W
-
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
0x17C
0x184
0x184
0x1A4
0x1A8
0x1A8
offset
0x174
0x178
0x180
0x188 -
0x1A0
0x1AC
0x1B0
0x1B4
0x1B8
0x1BC
0x1C0
0x1C4
0x1C8
0x1CC
0x1D0
0x1D4
Endpoint NAK Enable (device mode) 0x0000 0000
Port 1 status/control (device mode)
Port 1 status/control (host mode)
OTG status and control
USB device mode (device mode)
USB device mode (host mode)
Endpoint setup status
Endpoint de-initialization
Endpoint status
Endpoint control 3
Endpoint control 5
Description
Length of virtual frame
Endpoint NAK (device mode)
Reserved
Endpoint initialization
Endpoint complete
Endpoint control 0
Endpoint control 1
Endpoint control 2
Endpoint control 4
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 0000
0x0000 0000
-
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
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