LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 29

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
3.3.4.3 SPIFI boot mode
Figure 12
this mode happens only if the boot mode is set accordingly (see boot modes
Table
Boot ROM to support a SPI flash boot, the device should support “High frequency
continuous array read” (command 0x0B). Since the boot ROM doesn't rely on a response
for commands 0xAB, 0xB9 and 0x9F, as long as the SPI device ignores or responds
correctly to these commands, the LPC18xx will be able to boot from them.
Fig 11. UART boot process
8). The SPIFI clock is 36 MHz.
details the boot-flow steps of the Quad SPI flash boot mode. The execution of
All information provided in this document is subject to legal disclaimers.
UART0 P2_1, P2_0
Rev. 00.13 — 20 July 2011
Configuration
Setup Pin
Init UART assuming
FFAST_IN =12MHz
see main boot flow
1152000-8-n-1
character
= 0x3F?
transmit
receive
char
Chapter 3: LPC18xx Boot ROM
OK
yes
no
UM10430
© NXP B.V. 2011. All rights reserved.
Table 7
29 of 1164
and