LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 605

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.15 SCT flag enable register
24.6.16 SCT event flag register
Table 513. SCT DMA 0 request register (DMAREQ0 - address 0x4000 005C) bit description
Table 514. SCT DMA 1 request register (DMAREQ1 - address 0x4000 0060) bit description
This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag
register
Table 515. SCT flag enable register (EVEN - address 0x4000 00F0) bit description
This register records events. Writing ones to this register clears the corresponding flags
and will negate the SCT interrupt request if all enabled Flag bits are zero.
Table 516. SCT event flag register (EVFLAG - address 0x4000 00F4) bit description
Bit
15:0
29:16
30
31
Bit
15:0
29:16
30
31
Bit
15:0
31:16
Bit
15:0 FLAG
31:
16
Symbol Description
-
Symbol
IEN
-
(Section
Symbol
DEV_0
-
DRL0
DRQ0
Symbol
DEV_1
-
DRL1
DRQ1
Bit n is one if event n has occurred since reset or a 1 was last written to
this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
Reserved
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24.6.16) is also set.
Description
The SCT requests interrupt when bit n of this register and the event
flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event
15 = bit 15).
Reserved
Rev. 00.13 — 20 July 2011
Description
If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event
1 = bit 1,..., event 15 = bit 15).
Reserved
A 1 in this bit makes the SCT set DMA request 0 when it loads
the Match_L/Unified registers from the Reload_L/Unified
registers.
This read-only bit indicates the state of DMA Request 0
Description
If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event
1 = bit 1,..., event 15 = bit 15).
Reserved
A 1 in this bit makes the SCT set DMA request 1 when it loads
the Match L/Unified registers from the Reload L/Unified
registers.
This read-only bit indicates the state of DMA Request 1.
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
Reset
value
0
-
Reset
value
0
-
Reset
value
0
-