LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 391

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 331. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description
Table 332. USB Endpoint Setup Status register (ENDPTSETUPSTAT - address 0x4000 61AC) bit description
<Document ID>
User manual
Bit
4
5
31:6
Bit
5:0
31:6
Symbol Value
SDIS
VBPS
-
Symbol
ENDPTSET
UPSTAT
-
20.6.18 USB Endpoint Setup Status register (ENDPSETUPSTAT)
20.6.19 USB Endpoint Prime register (ENDPTPRIME)
0
1
0
1
-
Description
Setup endpoint status for logical endpoints 0 to 5.
For every setup transaction that is received, a corresponding bit in this register
is set to one. Software must clear or acknowledge the setup transfer by writing
a one to a respective bit after it has read the setup data from Queue head. The
response to a setup packet as in the order of operations and total response
time is crucial to limit bus time outs while the setup lockout mechanism is
engaged.
reserved
For each endpoint, software should write a one to the corresponding bit whenever posting
a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Remark: These bits will be momentarily set by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.
Description
Stream disable mode
Remark: The use of this feature substantially limits the overall USB
performance that can be achieved.
Not disabled
Disabled.
Setting to a ‘1’ ensures that overruns/underruns of the latency FIFO are
eliminated for low bandwidth systems where the RX and TX buffers are
sufficient to contain the entire packet. Enabling stream disable also has the
effect of ensuring the the TX latency is filled to capacity before the packet is
launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significant when stream
disable is active. See TXFILLTUNING to characterize the adjustments
needed for the scheduler when using this feature.
VBUS power select
vbus_pwr_select is set LOW.
vbus_pwr_select is set HIGH
reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Reset
value
0
-
UM10430
Reset
value
0
0
-
© NXP B.V. 2011. All rights reserved.
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