LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 960

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 905. Level configuration register (HILO - address 0x4004 4000) bit description
Bit
6
7
8
9
10
11
12
13
14
Symbol
BOD_L
WWDT_L
ETH_L
USB0_L
USB1_L
-
CAN_L
TIM2_L
TIM6_L
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0
1
-
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Level detect mode for BOD event.
Detect LOW level if bit 6 in the EDGE register is 0. Detect
falling edge if bit 6 in the EDGE register is 1.
Detect HIGH level if bit 6 in the EDGE register is 0. Detect
rising edge if bit 6 in the EDGE register is 1.
Level detect mode for WWDTD event.
Detect LOW level if bit 7 in the EDGE register is 0. Detect
falling edge if bit 7 in the EDGE register is 1.
Detect HIGH level if bit 7 in the EDGE register is 0. Detect
rising edge if bit 7 in the EDGE register is 1.
Level detect mode for ethernet event.
Detect LOW level if bit 8 in the EDGE register is 0. Detect
falling edge if bit 8 in the EDGE register is 1.
Detect HIGH level if bit 8 in the EDGE register is 0. Detect
rising edge if bit 8 in the EDGE register is 1.
Level detect mode for USB0 event.
Detect LOW level if bit 9 in the EDGE register is 0. Detect
falling edge if bit 9 in the EDGE register is 1.
Detect HIGH level if bit 9 in the EDGE register is 0. Detect
rising edge if bit 9 in the EDGE register is 1.
Level detect mode for USB1 event.
Detect LOW level if bit 10 in the EDGE register is 0. Detect
falling edge if bit 10 in the EDGE register is 1.
Detect HIGH level if bit 10 in the EDGE register is 0.
Detect rising edge if bit 10 in the EDGE register is 1.
Reserved.
Level detect mode for C_CAN event.
Detect LOW level if bit 12 in the EDGE register is 0. Detect
falling edge if bit 12 in the EDGE register is 1.
Detect HIGH level if bit 12 in the EDGE register is 0.
Detect rising edge if bit 12 in the EDGE register is 1.
Level detect mode for combined timer output 2 event.
Detect LOW level if bit 13 in the EDGE register is 0. Detect
falling edge if bit 13 in the EDGE register is 1.
Detect HIGH level if bit 13 in the EDGE register is 0.
Detect rising edge if bit 13 in the EDGE register is 1.
Level detect mode for combined timer output 6 event.
Detect LOW level if bit 14 in the EDGE register is 0. Detect
falling edge if bit 14 in the EDGE register is 1.
Detect HIGH level if bit 14 in the EDGE register is 0.
Detect rising edge if bit 14 in the EDGE register is 1.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0
0