LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 978

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 151. CGU and CCU0/1 block diagram
ENET_RX_CLK
ENET_TX_CLK
GP_CLK
RTCX1
RTCX2
XTAL1
XTAL2
42.4.2 Basic configuration
42.4.3 Features
42.4.4 General description
CGU
The CGU is configured as follows:
Table 925. CGU clocking and power control
The CGU generates multiple independent clocks for the core and the peripheral blocks of
the LPC18xx. Each independent clock is called a base clock and itself is one of the inputs
to the two Clock Control Units (CCUs) which control the branch clocks to the individual
peripherals (see
The CGU selects the inputs to the clock generators from multiple clock sources, controls
the clock generation, and routes the outputs of the clock generators through the clock
source bus to the output stages. Each output stage provides an independent clock source
and corresponds to one of the base clocks for the LPC18xx. See
description of each base clock and
clock.
CGU
•
•
•
•
•
•
CRYSTAL OSC
See
Do not reset the CGU during normal operation.
PLL0/1 control
Oscillator control
Clock generation and clock source multiplexing
Five integer dividers
12 MHz IRC
32 kHz OSC
Table 925
Base clock
BASE_M3_CLK
All information provided in this document is subject to legal disclaimers.
(USB0)
(AUDIO)
Chapter
PLL0
PLL0
PLL1
for clocking and power control.
Rev. 00.13 — 20 July 2011
14).
IDIVB
IDIVC
IDIVC
IDIVE
IDIVA
/256
/16
/16
/16
/4
OUTCLK1, 3 - 6, 9 - 10
(BASE_xxx_CLK)
BASE_SAFE_CLK
OUTCLK12 - 19
(BASE_xxx_CLK)
OUTCLK20
Table 928
OUTCLK11
OUTCLK7
OUTCLK8
Branch clock
CLK_M3_BUS
for the possible clock sources for each base
7
8
LCD_CLK
ENET_RX_CLK
WWDT
ENET_TX_CLK
CLKOUT
CCU1
CCU2
Table 926
Chapter 42: Appendix
Maximum frequency
150 MHz
UM10430
© NXP B.V. 2011. All rights reserved.
branch clocks to core
and peripherals
branch clocks to
peripherals
for a
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