LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 623

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
25.6 DMA connections
25.7 Register description
Table 533. Register overview: Timer0/1/2/3 (register base addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1),
<Document ID>
User manual
Name
IR
TCR
TC
PR
0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3))
Access Address
R/W
R/W
R/W
R/W
Table 531. Timer0/1/2/3 pin description
Table 532
Table 532. Timer/Counter function description
<tbd>
Each Timer/Counter contains the registers shown in
Function name
CTOUT_[11:8]
Timer3
CTIN_0
CTIN_6
CTIN_7
CTOUT_[15:12]
Pin
CAP0_[3:0]
CAP1_[3:0]
CAP2_[3:0]
CAP3_[3:0]
MAT0_[3:0]
MAT1_[3:0]
MAT2_[3:0]
MAT3_[3:0]
offset
0x000
0x004
0x008
0x00C
gives a brief summary of each of the Timer/Counter related pins.
Description
Interrupt Register. The IR can be written to clear interrupts. The IR can be
read to identify which of eight possible interrupt sources are pending.
Timer Control Register. The TCR is used to control the Timer Counter
functions. The Timer Counter can be disabled or reset through the TCR.
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK.
The TC is controlled through the TCR.
Prescale Register. The Prescale Counter (below) is equal to this value,
the next clock increments the TC and clears the PC.
Type
Input
Output
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Capture Signals- A transition on a capture pin can be configured to load
one of the Capture Registers with the value in the Timer Counter and
optionally generate an interrupt. Capture functionality can be selected
from a number of pins.
Timer/Counter block can select a capture signal as a clock source
instead of the PCLK derived clock . For more details see
Section
External Match Output - When a match register (MR3:0) equals the timer
counter (TC) this output can either toggle, go LOW, go HIGH, or do
nothing. The External Match Register (EMR) controls the functionality of
this output. Match Output functionality can be selected on a number of
pins in parallel.
Direction
O
I
I
I
O
25.7.11.
Description
MAT2_[3:0]; match outputs 3:0 of timer 2 are ORed with
SCT outputs 11 to 8.
CAP3_0; capture input 0 of timer 3.
CAP3_1; capture input 1 of timer 3.
CAP3_2; capture input 2 of timer 3.
MAT3_[3:0]; match outputs 3:0 of timer 3 are ORed with
SCT outputs 15 to 12.
Table
Chapter 25: LPC18xx Timer0/1/2/3
533.
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
[1]