LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 652

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.7.9.4 MCPWM Interrupt Flags read address
The INTF register includes all MCPWM interrupt flags, which are set when the
corresponding hardware event occurs, or when ones are written to the INTF_SET
address. When corresponding bits in this register and INTEN are both 1, the MCPWM
asserts its interrupt request to the Interrupt Controller module. This address is read-only,
but the bits in the underlying register can be modified by writing ones to addresses
INTF_SET and INTF_CLR.
Table 565. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description
Bit
0
1
2
3
4
5
6
7
Symbol
ILIM0_F
IMAT0_F
ICAP0_F
-
ILIM1_F
IMAT1_F
ICAP1_F
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Limit interrupt flag for channel 0.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Match interrupt flag for channel 0.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Capture interrupt flag for channel 0.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Reserved.
Limit interrupt flag for channel 1.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Match interrupt flag for channel 1.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Capture interrupt flag for channel 1.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Reserved.
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
652 of 1164
Reset
value
0
0
0
-
0
0
0
-