LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 756

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 701: UART1 Line Status Register (LSR - address 0x4008 2014) bit description
<Document ID>
User manual
Bit
0
1
2
Fig 96. Auto-CTS Functional Timing
UART1 TX
CTS1 pin
Symbol
RDR
OE
PE
33.5.10 UART1 Line Status Register
start
bits0..7
While starting transmission of the initial character the CTS1 signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets
de-asserted transmission resumes and a start bit is sent followed by the data bits of the
next character.
The U1LSR is a read-only register that provides status information on the UART1 TX and
RX blocks.
Value Description
0
1
0
1
0
1
stop
Receiver Data Ready.
U1LSR[0] is set when the U1RBR holds an unread character and is cleared when
the UART1 RBR FIFO is empty.
The UART1 receiver FIFO is empty.
The UART1 receiver FIFO is not empty.
Overrun Error.
The overrun error condition is set as soon as it occurs. An U1LSR read clears
U1LSR[1]. U1LSR[1] is set when UART1 RSR has a new character assembled
and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be
overwritten and the character in the UART1 RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
Parity Error.
When the parity bit of a received character is in the wrong state, a parity error
occurs. An U1LSR read clears U1LSR[2]. Time of parity error detection is
dependent on U1FCR[0].
Note: A parity error is associated with the character at the top of the UART1 RBR
FIFO.
Parity error status is inactive.
Parity error status is active.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
start
bits0..7
stop
Chapter 33: LPC18xx UART1
start
UM10430
© NXP B.V. 2011. All rights reserved.
bits0..7
756 of 1164
stop
Reset
value
0
0
0