LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 533

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.9.2 Receive descriptor
Table 440. Transmit descriptor word 3 (TDES3)
Table 441. Transmit descriptor word 6 (TDES6)
Table 442. Transmit descriptor word 7 (TDES7)
The structure of the received descriptor is shown in
descriptor data (8 DWORDs) when Advanced Timestamp or IPC Full Offload feature is
selected.
Remark: When either of these features is enabled, the SW should set the DMA Bus Mode
register[7] so that the DMA operates with extended descriptor size. When this control bit is
reset, RDES0[7] and RDES0[0] is always cleared and the RDES4-RDES7 descriptor
space are not valid.
Bit
31:0
Bit
31:0
Bit
31:0
Symbol Description
Symbol Description
TTSL
Symbol Description
TTSH
B2ADD
All information provided in this document is subject to legal disclaimers.
Buffer 2 Address Pointer (Next Descriptor Address)
Indicates the physical address of Buffer 2 when a descriptor ring structure is
used. If the Second Address Chained (TDES1[24]) bit is set, this address
contains the pointer to the physical memory where the Next Descriptor is
present. The buffer address pointer must be aligned to the bus width only
when TDES1[24] is set. (LSBs are ignored internally.)
Transmit Frame Timestamp Low
This field is updated by DMA with the least significant 32 bits of the
timestamp captured for the corresponding transmit frame. This field has the
timestamp only if the Last Segment bit (LS) in the descriptor is set and
Timestamp status (TTSS) bit is set.
Transmit Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the
timestamp captured for the corresponding receive frame. This field has the
timestamp only if the Last Segment bit (LS) in the descriptor is set and
Timestamp status (TTSS) bit is set.
Rev. 00.13 — 20 July 2011
Figure
Chapter 22: LPC18xx Ethernet
52. This can have 32 bytes of
UM10430
© NXP B.V. 2011. All rights reserved.
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