LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 253

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
15.5.1.3 Pin interrupt level (rising edge interrupt) set register
15.5.1.4 Pin interrupt level (rising edge interrupt) clear register
15.5.1.5 Pin interrupt active level (falling edge interrupt enable) register
For each of the 8 pin interrupts selected in the PINTSEL registers (see
Table
depending on the pin interrupt mode configured in the PINTMODE register:
Table 173. Pin interrupt level (rising edge interrupt) set register (SIENR, address 0x4008
For each of the 8 pin interrupts selected in the PINTSEL registers (see
Table
depending on the pin interrupt mode configured in the ISEL register:
Table 174. Pin interrupt level (rising edge interrupt) clear register (PCIENR, address 0x4008
For each of the 8 pin interrupts selected in the PINTSEL registers (see
Table
configures the level sensitivity depending on the pin interrupt mode configured in the ISEL
register:
Bit
7:0
31:8
Bit
7:0
31:8
•
•
•
•
•
•
If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
set.
If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set.
If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
cleared.
If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared.
If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
enabled.
If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level
interrupt (HIGH or LOW) is configured.
131), one bit in the SIENR register sets the corresponding bit in the IENR register
131), one bit in the CIENR register clears the corresponding bit in the IENR register
131), one bit in the PINTSEN_F register enables the falling edge interrupt or the
Symbol
SETENRL
-
Symbol
CENRL
-
7008) bit description
700C) bit description
All information provided in this document is subject to legal disclaimers.
Description
Ones written to this address clear bits in the IENR, thus
disabling the interrupts. Bit n clears bit n in the IENR
register.
0 = No operation.
1 = Disable rising edge or level interrupt.
Reserved.
Description
Ones written to this address set bits in the PINTEN_R,
thus enabling interrupts. Bit n sets bit n in the PINTEN_R
register.
0 = No operation.
1 = Enable rising edge or level interrupt.
Reserved.
Rev. 00.13 — 20 July 2011
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
Table 130
Table 130
Table 130
-
Reset
value
NA
Reset
value
NA
-
253 of 1164
Access
WO
-
Access
WO
-
and
and
and