LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 621

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

25.1 How to read this chapter
25.2 Basic configuration
25.3 Features
<Document ID>
User manual
The timers are available on all LPC18xx parts.
The following configuration options apply to parts LPC1850_30_20_10 Rev ‘A’ only:
The Timers are configured as follows:
Table 530. Timer0/1/2/3 clocking and power control
Clock to the timer0 register interface and
timer0 peripheral clock PCLK.
Clock to the timer1 register interface and
timer1 peripheral clock PCLK.
Clock to the timer2 register interface and
timer2 peripheral clock PCLK.
Clock to the timer3 register interface and
timer3 peripheral clock PCLK.
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UM10430
Chapter 25: LPC18xx Timer0/1/2/3
Rev. 00.13 — 20 July 2011
The timer capture inputs and match outputs are configured through the GIMA (see
Section
All timer capture inputs are also connected to dedicated external pins (see
Section 14.3
See
The Timer0/1/2/3 are reset by the TIMER0/1/2/3_RST (reset #32/33/34/35).
The Timer0/1/2/3 interrupts are connected to slot # 12/13/14/15 in the NVIC. Match
channels 2 of Timer0/1/3 are connected to slots # 13, 14, 16 in the Event router.
(These outputs are ORed with SCT outputs 2, 6, 14.)
For connecting the match channels 0 and 1 of Timer0/1/2/3 to the GPDMA, use the
DMAMUX register in the CREG block (see
in the DMA Channel Configuration registers
Inputs to Timer1/2/3 capture inputs are controlled by the CREG6 register in the CREG
block (see
The timer capture inputs and match outputs are configured through the GIMA (see
Section
All timer capture inputs are also connected to dedicated external pins (see
Section 14.3
A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
Table 530
14.3).
14.3).
Table
All information provided in this document is subject to legal disclaimers.
and
and
for clocking and power control.
37).
Section
Section
Rev. 00.13 — 20 July 2011
13.3.6).
13.3.6).
Base clock
BASE_M3_CLK
BASE_M3_CLK
BASE_M3_CLK
BASE_M3_CLK
Table
(Section
35) and enable the GPDMA channel
Branch clock
CLK_M3_TIMER0 150 MHz
CLK_M3_TIMER1 150 MHz
CLK_M3_TIMER2 150 MHz
CLK_M3_TIMER3 150 MHz
16.6.20).
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
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