LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 684
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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28.1 How to read this chapter
28.2 Basic configuration
28.3 Features
28.4 General description
<Document ID>
User manual
The RIT is available on all LPC18xx parts.
The RIT is configured as follows:
Table 605. RIT clocking and power control
The Repetitive Interrupt Timer provides a versatile means of generating interrupts at
specified time intervals, without using a standard timer. It is intended for repeating
interrupts that aren’t related to Operating System interrupts. However, it could be used as
an alternative to the Cortex-M3 System Tick Timer if there are different system
requirements.
Clock to the RI timer register interface and
RI timer peripheral clock.
•
•
•
•
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UM10430
Chapter 28: LPC18xx Repetitive Interrupt Timer (RIT)
Rev. 00.13 — 20 July 2011
See
The RIT is reset by the RITIMER_RST (reset #36).
The RIT interrupt is connected to slot # 11 in the NVIC.
32-bit counter running from PCLK. Counter can be free-running, or be reset by a
generated interrupt.
32-bit compare value.
32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
Table 605
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_M3_CLK
Branch clock
CLK_M3_RITIMER
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
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