LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 376

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 320. USB TT Control register in host mode (TTCTRL - address 0x4000 615C) bit description
Table 321. USB burst size register (BURSTSIZE - address 0x4000 6160) bit description - device/host mode
<Document ID>
User manual
Bit
23:0
30:24 TTHA
31
Bit
7:0
15:8
31:16 -
Symbol
-
-
Symbol
RXPBURST
TXPBURST
20.6.11.1 Device controller
20.6.11.2 Host controller
20.6.9.2 Host mode
20.6.10 Burst Size register (BURSTSIZE)
20.6.11 Transfer buffer Fill Tuning register (TXFILLTUNING)
This register contains parameters needed for internal TT operations. This register is used
by the host controller only. Writes must be in Dwords.
This register is used to control and dynamically change the burst size used during data
movement on the master interface of the USB DMA controller. Writes must be in Dwords.
The default for the length of a burst of 32-bit words for RX and TX DMA data transfers is
16 words each.
This register is not used in device mode.
The fields in this register control performance tuning associated with how the host
controller posts data to the TX latency FIFO before moving the data onto the USB bus.
The specific areas of performance include the how much data to post into the FIFO and
an estimate for how long that operation should take in the target system.
Definitions:
Description
Reserved.
Hub address when FS or LS device are connected directly.
Reserved.
Description
Programmable RX burst length
This register represents the maximum length of a burst in 32-bit words while
moving data from the USB bus to system memory.
Programmable TX burst length
This register represents the maximum length of a burst in 32-bit words while
moving data from system memory to the USB bus.
Reserved.
T
T
T
T
T
0
1
ff
s
p
= Total packet flight time (send-only) packet; T
= Standard packet overhead
= Time to send data payload
= Time to fetch packet into TX FIFO up to specified level
= Total packet time (fetch and send) packet; T
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
p
s
= T
= T
ff
0
+ T
+ T
0
1
+ T
1
UM10430
© NXP B.V. 2011. All rights reserved.
N/A
Reset
value
0
0
Reset
value
0x10
0x10
-
376 of 1164
Access
-
R/W
Access
R/W
R/W
-