LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 295

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
17.5 Pin description
Table 221. SPIFI Pin description
17.6 SPIFI API calls
<Document ID>
User manual
Pin
SPIFI_SCK
SPIFI_CS
SPIFI_MOSI or IO0
SPIFI_MISO or IO1
SPIFI_SIO[3:2]
Direction
O
O
I/O
I/O
I/O
Table 220. SPIFI flash memory map
Commands are divided into fields called opcode, address, intermediate, and data. The
address, intermediate, and data fields are optional depending on the opcode. Some
devices include a mode in which the opcode can be implied in read commands for higher
performance. Data fields are further divided into input and output data fields depending on
the opcode.
Remark: Flashless parts (LPC1850/30/20/10) can use the SPIFI for booting. See
Section
The SPIFI interface is controlled through a set of simple API calls located in the LPC18xx
ROM.
Memory
SPIFI data
3.3.4.3.
Description
Serial clock for the flash memory, switched only during active bits on the MOSI/IO0,
MISO/IO1, and IO3:2 lines.
Chip select for the flash memory, driven low while a command is in progress, and high
between commands. In the typical case of one serial slave, this signal can be
connected directly to the device. If more than one serial slave is connected, software
and off-chip hardware should use general-purpose I/O signals in combination with this
signal to generate the chip selects for the various slaves.
This is an output except in quad/dual input data fields. After a quad/dual input data field,
it becomes an output again one serial clock period after CS goes high.
This is an output in quad/dual opcode, address, intermediate, and output data fields,
and an input in SPI mode and in quad/dual input data fields. After an input data field in
quad/dual mode, it becomes an output again one serial clock period after CS goes
high.
These are outputs in quad opcode, address, intermediate, and output data fields, and
inputs in quad input data fields. If the flash memory does not have quad capability,
these pins can be assigned to GPIO or other functions.
Address
0x1400 0000 to 0x17FF FFFF
0x8000 0000 to 0x87FF FFFF
Remark: These are the spaces allocated to the SPIFI in the LPC18xx. The same
data appears in the first area and the first half of the second area. These areas
allow maxima of 64 and 128 MB of SPI flash (respectively) to be mapped into the
Cortex-M3 memory space. In practice, the usable space is limited to the size of the
connected device
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 17: LPC18xx SPI Flash Interface (SPIFI)
UM10430
© NXP B.V. 2011. All rights reserved.
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