LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1090

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 171. Block diagram of a message object transfer
APB
bus
42.10.6.2 Message interface registers
IF1 COMMAND REQUEST
IF2 COMMAND REQUEST
COMMAND REGISTERS
IF1 COMMAND MASK
IF2 COMMAND MASK
IF1 ARBITRATION 1/2
MESSAGE BUFFER
IF2 ARBITRATION 1/2
IF1 MESSAGE CTRL
IF2 MESSAGE CTRL
IF1 DATA A1/2
IF1 DATA B1/2
IF1 MASK1, 2
IF2 DATA A1/2
IF2 DATA B1/2
REGISTERS
IF2 MASK1, 2
INTERFACE
There are two sets of interface registers which are used to control the CPU access to the
Message RAM. The interface registers avoid conflicts between CPU access to the
Message RAM and CAN message reception and transmission by buffering the data to be
transferred. A complete Message Object (see
Message Object may be transferred between the Message RAM and the IFx Message
Buffer registers in one single transfer.
The function of the two interface register sets is identical (except for test mode Basic).
One set of registers may be used for data transfer to the Message RAM while the other
set of registers may be used for the data transfer from the Message RAM, allowing both
processes to be interrupted by each other.
Each set of interface registers consists of message buffer registers controlled by their own
command registers. The command mask register specifies the direction of the data
transfer and which parts of a message object will be transferred. The command request
register is used to select a message object in the message RAM as target or source for
the transfer and to start the action specified in the command mask register.
message object
All information provided in this document is subject to legal disclaimers.
read transfer
transfer a
write transfer
Rev. 00.13 — 20 July 2011
TRANSMISSION REQUEST 1/2
INTERRUPT PENDING1/2
MESSAGE OBJECT 32
MESSAGE OBJECT 1
MESSAGE OBJECT 2
MESSAGE HANDLER
MESSAGE VALID1/2
MESSAGE RAM
NEW DATA 1/2
.
.
.
Section
42.10.6.2.1) or parts of the
SHIFT REGISTERS
CAN CORE/
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
CAN frame
transfer a
receive
transmit
1090 of 1164
CAN
bus