LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 316

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 249. Transferred Host to BIU-FIFO Byte Count Register (TBBCNT, address 0x4000 4060) bit description
<Document ID>
User manual
Bit
31:0
Symbol
TRANS_FIFO_BYTE_
COUNT
18.6.25 Transferred Host to BIU-FIFO Byte Count Register (TBBCNT)
18.6.26 Debounce Count Register (DEBNCE)
18.6.27 User ID Register (USRID)
18.6.28 Version ID Register (VERID)
Table 250. Debounce Count Register (DEBNCE, address 0x4000 4064) bit description
Table 251. User ID Register (USRID, address 0x4000 4068) bit description
Table 252. Version ID Register (VERID, address 0x4000 406C) bit description
Bit
23:0
31:24
Bit
31:0
Bit
31:0
Description
Number of bytes transferred between Host/DMA memory and BIU FIFO. In 32-bit
or 64-bit AMBA data-bus-width modes, register should be accessed in full to
avoid read-coherency problems. In 16-bit AMBA data-bus-width mode, internal
16-bit coherency register is implemented. User should first read lower 16 bits and
then higher 16 bits. When reading lower 16 bits, higher 16 bits of counter are
stored in temporary register. When higher 16 bits are read, data from temporary
register is supplied. Both TCBCNT and TBBCNT share same coherency register.
Symbol
VERID
Symbol
USRID
Symbol
DEBOUNCE_CO
UNT
-
All information provided in this document is subject to legal disclaimers.
Description
User identification register; value set by user. Default reset value
can be picked by user while configuring core before synthesis.
Can also be used as scratch pad register by user.
Description
Version identification register; register value is
hard-wired. Can be read by firmware to support different
versions of core.
Rev. 00.13 — 20 July 2011
Description
Number of host clocks (clk) used by debounce filter
logic; typical debounce time is 5-25 ms.
Reserved
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x5342230a
Reset
value
0xFFFFFF
Reset
value
NA
316 of 1164
Reset
value
0