LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1141

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 972. EMC data out delay register (EMCDOUTDELAY,
Table 973. EMC DQM delay register (EMCFBCLKDELAY,
Table 974. EMC address delay register 0
Table 975. EMC address delay register 1
Table 976. EMC address delay register 2
Table 977. EMC data in delay register 3 (EMCDINDELAY,
Table 978. GPIO clocking and power control . . . . . . . .1054
Table 979. GPIO pin description . . . . . . . . . . . . . . . . . .1054
Table 980. Register overview: GPIO (register base address:
Table 981. GPIO port direction register (DIR0 to DIR4 -
Table 982. GPIO port direction control byte and halfword
Table 983. GPIO port mask register (MASK0 to MASK4 -
Table 984. GPIO port mask byte and half-word accessible
Table 985. GPIO port pin value register (PIN0 to PIN0 -
Table 986. GPIO port pin value byte and half-word
Table 987. GPIO port output set register (SET0 to SET4 -
Table 988. GPIO port output set byte and half-word
Table 989. GPIO port output clear register (CLR0 to CLR4 -
Table 990. GPIO port output clear byte and half-word
Table 991. I2S clocking and power control . . . . . . . . . .1062
Table 992. Pin description . . . . . . . . . . . . . . . . . . . . . . .1064
Table 993. Register overview: I2S (base address 0x400A
Table 994. I2S Digital Audio Output register (DAO - address
Table 995. I2S Digital Audio Input register (DAI - address
Table 996. Transmit FIFO register (TXFIFO - address
Table 997. I2S Receive FIFO register (RXFIFO - address
Table 998. I2S Status Feedback register (STATE - address
<Document ID>
User manual
address 0x4008 6D0C) bit description . . . .1050
address 0x4008 6D10) bit description . . . .1051
(EMCADDRDELAY0, address 0x4008 6D14) bit
description . . . . . . . . . . . . . . . . . . . . . . . . .1051
(EMCADDRDELAY1, address 0x4008 6D18) bit
description . . . . . . . . . . . . . . . . . . . . . . . . .1052
(EMCADDRDELAY2, address 0x4008 6D1C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . .1053
address 0x4008 6D24) bit description . . . .1053
0x400F 0000) . . . . . . . . . . . . . . . . . . . . . . .1055
addresses 0x400F 0000 to 0x400F 0080) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .1056
accessible register view . . . . . . . . . . . . . . . .1057
addresses 0x400F 0010 to 0x400F 0090) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .1057
register description . . . . . . . . . . . . . . . . . . . .1058
addresses 0x400F 0014 to 0x400F 0094) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .1059
accessible register description . . . . . . . . . . .1059
addresses 0x400F 0018 to 0x400F 0098) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .1060
accessible register description . . . . . . . . . . .1060
0x400F 001C to 0x400F 009C) bit description . . .
1061
accessible register description . . . . . . . . . . .1061
2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1066
0x400A 2000) bit description . . . . . . . . . . . .1067
0x400A 2004) bit description . . . . . . . . . . . .1067
0x400A 2008) bit description . . . . . . . . . . . .1068
0x400A 200C) bit description . . . . . . . . . . . .1068
0x400A 2010) bit description . . . . . . . . . . . .1068
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 999. I2S DMA Configuration register 1 (DMA1 -
Table 1000. I2S DMA Configuration register 2 (DMA2 -
Table 1001. I2S Interrupt Request Control register (IRQ -
Table 1002. I2S Transmit Clock Rate register (TXRATE -
Table 1003. I2S Receive Clock Rate register (RXRATE -
Table 1004. I2S Transmit Clock Rate register (TXBITRATE -
Table 1005. I2S Receive Clock Rate register (RXBITRATE -
Table 1006. I2S Transmit Mode Control register (TXMODE -
Table 1007. I2S Receive Mode Control register (RXMODE -
Table 1008. I2S transmit modes . . . . . . . . . . . . . . . . . . 1074
Table 1009. I2S receive modes . . . . . . . . . . . . . . . . . . 1076
Table 1010. Conditions for FIFO level comparison . . . . 1079
Table 1011. DMA and interrupt request generation . . . 1079
Table 1012. Status feedback in the STATE register . . . 1079
Table 1013. C_CAN clocking and power control . . . . . 1080
Table 1014. C_CAN pin description . . . . . . . . . . . . . . . 1082
Table 1015. Register overview: C_CAN0 (base address
Table 1016. CAN control registers (CNTL, address
Table 1017. CAN status register (STAT, address
Table 1018. CAN error counter (EC, address 0x400E 2008)
Table 1019. CAN bit timing register (BT, address
Table 1020. CAN interrupt register (INT, address
Table 1021. CAN test register (TEST, address 0x400E 2014)
Table 1022. CAN baud rate prescaler extension register
Table 1023. Message interface registers . . . . . . . . . . . 1091
Table 1024. Structure of a message object in the message
Table 1025. CAN message interface command request
Table 1026. CAN message interface command mask
Table 1027. CAN message interface command mask
address 0x400A 2014) bit description . . . . . 1069
address 0x400A 2018) bit description . . . . . 1069
address 0x400A 201C) bit description . . . . . 1069
address 0x400A 2020) bit description . . . . . 1070
address 0x400A 2024) bit description . . . . . 1071
address 0x400A 2028) bit description . . . . . 1071
address 0x400A 202C) bit description . . . . . 1072
address 0x400A 2030) bit description . . . . . 1072
address 0x400A 2034) bit description . . . . . 1072
0x400E 2000). . . . . . . . . . . . . . . . . . . . . . . . 1083
0x400E 2000) bit description
0x400E 2004) bit description
bit description . . . . . . . . . . . . . . . . . . . . . . . 1087
0x400E 200C) bit description. . . . . . . . . . . . 1088
0x400E 2010) bit description . . . . . . . . . . . . 1088
bit description. . . . . . . . . . . . . . . . . . . . . . . . 1089
(BRPE, address 0x400E 2018) bit description. . .
1089
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
registers (IF1_CMDREQ, address 0x400E 2020
and IF2_CMDREQ, address 0x400E 2080) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
registers write direction (IF1_CMDMSK, address
0x400E 2024 and IF2_CMDMSK, address
0x400E 2084) bit description . . . . . . . . . . . 1092
registers read direction (IF1_CMDMSK, address
0x400E 2024 and IF2_CMDMSK, address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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