LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 277

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 214. DMA Channel Control registers (CCONTROL, 0x4000 210C (C0CONTROL) to 0x4000 21EC (C7CONTROL))
<Document ID>
User manual
Bit
14:12
17:15
20:18
23:21
bit description
Symbol
SBSIZE
DBSIZE
SWIDTH
DWIDTH
…continued
Value Description
0x0
0x1
0x2
0x3
0x4
0x4
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x4
0x6
0x7
0x0
0x1
0x2
0x0
0x1
0x2
Source burst size. Indicates the number of transfers that make
up a source burst. This value must be set to the burst size of the
source peripheral, or if the source is memory, to the memory
boundary size (see
data that is transferred when the BREQ signal goes active in the
source peripheral.
Source burst size = 1
Source burst size = 4
Source burst size = 8
Source burst size = 16
Source burst size = 32
Source burst size = 64
Source burst size = 128
Source burst size = 256
Destination burst size. Indicates the number of transfers that
make up a destination burst transfer request. This value must
be set to the burst size of the destination peripheral or, if the
destination is memory, to the memory boundary size. The burst
size is the amount of data that is transferred when the BREQ
signal goes active in the destination peripheral.
Destination burst size = 1
Destination burst size = 4
Destination burst size = 8
Destination burst size = 16
Destination burst size = 32
Destination burst size = 64
Destination burst size = 128
Destination burst size = 256
Source transfer width. Transfers wider than the AHB master bus
width are illegal. The source and destination widths can be
different from each other. The hardware automatically packs
and unpacks the data as required. 0x3 to 0x7 - Reserved.
Byte (8-bit)
Halfword (16-bit)
Word (32-bit)
Destination transfer width. Transfers wider than the AHB master
bus width are not supported. The source and destination widths
can be different from each other. The hardware automatically
packs and unpacks the data as required. 0x3 to 0x7 - Reserved.
Byte (8-bit)
Halfword (16-bit)
Word (32-bit)
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Figure
5). The burst size is the amount of
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x0
0x0
0x0
0x0
277 of 1164
Access
R/W
R/W
R/W
R/W