LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 538

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 446. Receive descriptor fields 3 (RDES3)
The extended status written is as shown in
when there is status related to IPC or timestamp available. The availability of extended
status is indicated by bit-0 of RDES0. This status is available only when Advance
Timestamp or IPC Full Offload feature is selected.
Table 447. Receive descriptor fields 4 (RDES4)
Bit
31:0
Bit
2:0
3
4
5
Symbol
B2ADD
Symbol
IPPL
IPHE
IPPLE
IPCSB
All information provided in this document is subject to legal disclaimers.
Description
Buffer 2 Address Pointer (Next Descriptor Address)
These bits indicate the physical address of Buffer 2 when a descriptor ring
structure is used. If the Second Address Chained (RDES1[24]) bit is set, this
address contains the pointer to the physical memory where the Next
Descriptor is present. If RDES1[24] is set, the buffer (Next Descriptor)
address pointer must be bus width-aligned (RDES3[3, 2, or 1:0] = 0,
corresponding to a bus width of 128, 64, or 32. LSBs are ignored internally.)
However, when RDES1[24] is reset, there are no limitations on the RDES3
value, except for the following condition: The DMA uses the configured value
for its buffer address generation when the RDES3 value is used to store the
start of frame. The DMA ignores RDES3 [3, 2, or 1:0] (corresponding to a
bus width of 128, 64, or 32) if the address pointer is to a buffer where the
middle or last part of the frame is stored.
Description
IP Payload Type
These bits indicate the type of payload encapsulated in the IP datagram
processed by the Receive Checksum Offload Engine (COE). The COE also
sets these bits to 00 if it does not process the IP datagram’s payload due to
an IP header error or fragmented IP.
• 000: Unknown or did not process IP payload
• 001: UDP
• 010: TCP
• 011: ICMP
• 1xx: Reserved
IP Header Error
When set, this bit indicates either that the 16-bit IPv4 header checksum
calculated by the core does not match the received checksum bytes, or that
the IP datagram version is not consistent with the Ethernet Type value.
IP Payload Error
When set, this bit indicates that the 16-bit IP payload checksum (that is, the
TCP, UDP, or ICMP checksum) that the core calculated does not match the
corresponding checksum field in the received segment. It is also set when
the TCP, UDP, or ICMP segment length does not match the payload length
value in the IP Header field.
IP Checksum Bypassed
When set, this bit indicates that the checksum offload engine is bypassed.
Rev. 00.13 — 20 July 2011
Table
447. The extended status is written only
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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