LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 63

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
8.2.3 Deep-sleep mode
8.2.4 Power-down mode
8.2.5 Deep power-down
As in active mode, low-power and normal modes can be selected.
In Deep-sleep mode the CPU clock and peripheral clocks are shut down to save power;
logic states and SRAM memory are maintained. All analog blocks and the BOD control
circuit are powered down. The Deep-sleep mode is entered by a WFI or WFE instruction if
the SLEEPDEEP bit in the ARM Cortex-M3 system control register is set to 1 and the
PD0_SLEEP0_MODE register (see
value.
When the LPC18xx wakes up from Deep-sleep mode, the 12 MHz IRC is used as the
clock source for all base clocks.
Remark: Before entering Deep-sleep mode, program the CGU as follows:
Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and
minimizes power consumption during Deep-sleep mode.
In Power-down mode the CPU clock and peripheral clocks are shut down but logic states
are maintained. All SRAM memory except for the upper 8 kB of the local SRAM located at
0x1008 0000, all analog blocks, and the BOD control circuit are powered down.The
Power-down mode is entered by a WFI or WFE instruction if the SLEEPDEEP bit in the
ARM Cortex-M3 system control register is set to 1 and the PD0_SLEEP0_MODE register
(see
When the LPC18xx wakes up from Power-down mode, the 12 MHz IRC is used as the
clock source for all base clocks.
Remark: Before entering Power-down mode, program the CGU as follows:
Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and
minimizes power consumption during Power-down mode.
In Deep power-down mode the entire core logic is powered down. Only the logic in the
RTC power domain remains active. The Deep power-down mode is entered by a WFI or
WFE instruction if the SLEEPDEEP bit in the ARM Cortex-M3 system control register is
set to 1 and the PD0_SLEEP0_MODE register (see
Deep power-down value.
When the LPC18xx wakes up from Deep power-down mode, the boot loader configures
the PLL1 as the clock source running at 72 MHz.
•
•
•
•
Switch the clock source of all base clocks to the IRC.
Put the PLLs in power-down mode.
Switch the clock source of all base clocks to the IRC.
Put the PLLs in power-down mode.
Table
41) is programmed with the Power-down mode value.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 8: LPC18xx Power Management Controller (PMC)
Table
41) is programmed with the Deep-sleep mode
Table
41) is programmed with the
UM10430
© NXP B.V. 2011. All rights reserved.
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