LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 362

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 306. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description
<Document ID>
User manual
Bit
0
Symbol
RS
20.6.3.1 Device mode
20.6.3 USB Command register (USBCMD)
Value
0
1
Table 303. HCCPARAMS register (HCCPARAMS - address 0x4000 6108) bit description
Table 304. DCIVERSION register (DCIVERSION - address 0x4000 6120) bit description
Table 305. DCCPARAMS (address 0x4000 6124)
The host/device controller executes the command indicated in this register.
Bit
7:4
15:8
31:9
Bit
15:0
Bit
4:0
6:5
7
8
31:9
Description
Run/Stop
Writing a 0 to this bit will cause a detach event.
Writing a one to this bit will cause the device controller to enable a pull-up
on USB_DP and initiate an attach event. This control bit is not directly
connected to the pull-up enable, as the pull-up will become disabled upon
transitioning into high-speed mode. Software should use this bit to prevent
an attach event before the device controller has been properly initialized.
Symbol
IST
Symbol
Symbol
DEN
-
DC
HC
-
EECP
-
DCIVERSION The device controller interface conforms to the
All information provided in this document is subject to legal disclaimers.
Description
Device Endpoint Number.
These bits are reserved and should be set to zero.
Device Capable.
Host Capable.
These bits are reserved and should be set to zero.
Description
Isochronous Scheduling Threshold. This field indicates,
relative to the current position of the executing host
controller, where software can reliably update the
isochronous schedule.
EHCI Extended Capabilities Pointer. This optional field
indicates the existence of a capabilities list.
These bits are reserved and should be set to zero.
Rev. 00.13 — 20 July 2011
Description
two-byte BCD encoding of the interface version
number contained in this register.
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Reset value Access
0x4
-
0x1
0x1
-
UM10430
© NXP B.V. 2011. All rights reserved.
Access
R/W
Reset
value
0x1
Reset
value
0
0
-
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RO
-
RO
RO
-
Access
RO
Access
RO
RO
-
Reset
value
0