LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 283

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 217. Endian behavior
<Document ID>
User manual
Source
endian
Little
Little
Little
Little
16.7.1.6.1 Bus and transfer widths
16.7.1.6.2 Endian behavior
16.7.1.6 AHB master interface
Destination
endian
Little
Little
Little
Little
The DMA Controller contains two AHB master interfaces. Each AHB master is capable of
dealing with all types of AHB transactions, including:
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths and can be the same width or narrower than the physical bus width. The
DMA Controller packs or unpacks data as appropriate.
The DMA Controller can cope with both little-endian and big-endian addressing. Software
can set the endianness of each AHB master individually.
Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32-bit data
bus is observed.
Note: If byte swapping is not required, then use of different endianness between the
source and destination addresses must be avoided.
different source and destination combinations.
•
•
•
Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the DMA Controller stalls and waits until the transaction can complete.
Locked transfers for source and destination of each stream.
Setting of protection bits for transfers on each stream.
Source
width
8
8
8
16
All information provided in this document is subject to legal disclaimers.
Destination
width
8
16
32
8
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Source
transfer
no/byte lane
1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
1/[7:0]
1/[15:8]
2/[23:16]
2/[31:24]
Source data Destination
21
43
65
87
21
43
65
87
21
43
65
87
21
43
65
87
Table 217
transfer
no/byte lane
1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
1/[15:0]
2/[31:16]
1/[31:0]
1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
shows endian behavior for
UM10430
© NXP B.V. 2011. All rights reserved.
Destination data
21212121
43434343
65656565
87878787
43214321
87658765
87654321
21212121
43434343
65656565
87878787
283 of 1164