LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 532

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 437. Transmit descriptor word 0 (TDES0)
Table 438. Transmit descriptor word 1 (TDES1)
Table 439. Transmit descriptor word 2 (TDES2)
Bit
26
27
28
29
30
31
Bit
12:0
15:13
28:16
31:29
Bit
31:0
Symbol
DP
DC
FS
LS
IC
OWN
Symbol Description
Symbol Description
B1ADD
TBS1
-
TBS2
-
All information provided in this document is subject to legal disclaimers.
Transmit buffer 1 size
These bits indicate the first data buffer byte size, in bytes. If this field is 0, the
DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending
on the value of TCH (TDES0[20]).
Reserved
These bits indicate the second data buffer size in bytes. This field is not valid
if TDES0[20] is set. See
Reserved
Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There is no limitation on
the buffer address alignment. See
address alignment.
Description
Disable Pad
When set, the MAC does not automatically add padding to a frame shorter
than 64 bytes. When this bit is reset, the DMA automatically adds padding
and CRC to a frame shorter than 64 bytes, and the CRC field is added
despite the state of the DC (TDES0[27]) bit. This is valid only when the first
segment (TDES0[28]) is set.
Disable CRC
When this bit is set, the MAC does not append a cyclic redundancy check
(CRC) to the end of the transmitted frame. This is valid only when the first
segment (TDES0[28]) is set.
First Segment
When set, this bit indicates that the buffer contains the first segment of a
frame.
Last Segment
When set, this bit indicates that the buffer contains the last segment of the
frame. When this bit is set, the TBS1: Transmit Buffer 1 Size or TBS2:
Transmit Buffer 2 Size field in TDES1 should have a non-zero value.
Interrupt on Completion
When set, this bit sets the Transmit Interrupt (Register 5[0]) after the present
frame has been transmitted.
Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When
this bit is reset, it indicates that the descriptor is owned by the Host. The
DMA clears this bit either when it completes the frame transmission or when
the buffers allocated in the descriptor are read completely. The ownership bit
of the frame’s first descriptor must be set after all subsequent descriptors
belonging to the same frame have been set. This avoids a possible race
condition between fetching a descriptor and the driver setting an ownership
bit.
Rev. 00.13 — 20 July 2011
Section
22.8.1.3.
Section 22.8.1.2
Chapter 22: LPC18xx Ethernet
for further detail on buffer
UM10430
© NXP B.V. 2011. All rights reserved.
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