LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 39

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 14.
<Document ID>
User manual
Name
ICER1
ISPR0
ISPR1
ICPR0
ICPR1
IABR0
IABR1
IPR0
IPR1
IPR2
IPR3
IPR4
IPR5
IPR6
IPR7
STIR
Access Address
RW
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
WO
Register overview: NVIC (base address 0xE000 E000)
offset
0x184
0x200
0x204
0x280
0x284
0x300
0x304
0x400
0x404
0x408
0x40C
0x410
0x414
0x418
0x41C
0xF00
Interrupt Clear-Enable Register 1. This register allows disabling interrupts and
Interrupt Set-Pending Register 0. This register allows changing the interrupt
Interrupt Set-Pending Register 1. This register allows changing the interrupt
Interrupt Clear-Pending Register 0. This register allows changing the interrupt
Interrupt Clear-Pending Register 0. This register allows changing the interrupt
Description
reading back the interrupt enables for specific peripheral functions.
state to pending and reading back the interrupt pending state for specific
peripheral functions.
state to pending and reading back the interrupt pending state for specific
peripheral functions.
state to not pending and reading back the interrupt pending state for specific
peripheral functions.
state to not pending and reading back the interrupt pending state for specific
peripheral functions.
Interrupt Active Bit Register 0. This register allows reading the current interrupt
active state for specific peripheral functions.
Interrupt Active Bit Register 1. This register allows reading the current interrupt
active state for specific peripheral functions.
Interrupt Priority Registers 0. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 1 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 2. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 3. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 4. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 5. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 6. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 7. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Software Trigger Interrupt Register. This register allows software to generate an
interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
…continued
Chapter 5: LPC18xx NVIC
UM10430
© NXP B.V. 2011. All rights reserved.
39 of 1164
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0