LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 926

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
40.9.1 Prepare sector(s) for write operation
returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned
indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM
suggested scheme is used for the parameter passing/returning then it might create
problems due to difference in the C compiler implementation from different vendors. The
suggested parameter passing scheme reduces such risk.
The flash memory is not accessible during a write or erase operation. IAP commands,
which results in a flash write/erase operation, use 32 bytes of space in the top portion of
the on-chip RAM for execution. The user program should not be use this space if IAP flash
programming is permitted in the application.
Table 861. IAP Command Summary
This command makes flash write/erase operation a two step process.
IAP Command
Prepare sector(s) for write operation
Copy RAM to Flash
Erase sector(s)
Blank check sector(s)
Read part ID
Read Boot Code version
Read device serial number
Compare
Reinvoke ISP
Fig 149. IAP parameter passing
ARM REGISTER r0
ARM REGISTER r1
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 40: LPC18xx flash programming interface
Command Code
50
51
52
53
54
55
58
56
57
10
10
10
10
10
10
10
10
10
COMMAND CODE
PARAMETER 1
PARAMETER 2
PARAMETER n
STATUS CODE
RESULT 1
RESULT 2
RESULT n
Described in
Table 862
Table 863
Table 864
Table 865
Table 866
Table 867
Table 868
Table 869
Table 870
UM10430
command
parameter table
command
result table
© NXP B.V. 2011. All rights reserved.
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