LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 345

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 293. Static Memory Turn Round Delay registers (STATICWAITTURN, address
To prevent bus contention on the external memory data bus, the WAITTURN field controls
the number of bus turnaround cycles added between static memory read and write
accesses. The WAITTURN field also controls the number of turnaround cycles between
static memory and dynamic memory accesses.
Bit
3:0
31:4
Symbol
WAITTURN Bus turnaround cycles.
-
0x4000 5218 (STATICWAITTURN0), 0x4000 5238 (STATICWAITTURN1),
0x4000 5258 (STATICWAITTURN2), 0x4000 5278 (STATICWAITTURN3)) bit
description
All information provided in this document is subject to legal disclaimers.
Description
0x0 - 0xE = (n + 1) CCLK turnaround cycles. Bus turnaround time is
(WAITTURN + 1) x tCCLK.
0xF = 16 CCLK turnaround cycles (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0xF
-