LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 436

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.11.4 Susp_CTRL module
The SUSP_CTRL module implements the power management logic of USB-OTG. It
controls the suspend input of the transceiver. Asserting this suspend signal will put the
transceiver in suspend mode and the generation of the 30 MHz clock and 60 MHz clock
will be switched off.
A suspend control input of the transceiver (otg_on) that was previously tied high and
prevented the transceiver to go into full suspend mode, has been connected to <tbd>.
This bit is low by default and only needs to be set high in OTG Host mode operation.
In suspend mode, the transceiver will raise an output signal indicating that the PLL
generating the 480 MHz clock can be switched off.
The SUSP_CTRL module also generates an output signal indicating whether the AHB
clock is needed or not. If '0' the AHB clock is allowed to be switched off or reduced in
frequency in order to save power.
The core will enter the low power state if:
When operating in host mode, the core will leave the low power state on one of the
following conditions:
When operating in device mode, the core will leave the low power state on one of the
following conditions:
The vbusvalid and bvalid signals coming from the transceiver are not filtered in the
SUSP_CTRL module. Any change on those signals will cause a wake-up event.
Input signals 'host_wakeup_n' and 'dev_wakeup_n' are extra external wake-up signals
(for host mode and device mode respectively). However the detection of all USB related
wake-up events is already handled in the SUSP_CTRL mode. Therefore in normal
situations these signals can be tied high (= inactive).
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Software sets the PORTSC.PHCD bit.
software clears the PORTSC.PHCD bit
a device is connected and the PORTSC.WKCN bit is set
a device is disconnected an the PORTSC.WKDC bit is set
an over-current condition occurs and the PORTSC.WKOC bit is set
a remote wake-up from the attached device occurs (when USB bus was in suspend)
a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed)
a change on bvalid occurs (=VBUS threshold at 4.0 V is crossed).
software clears the PORTSC.PHCD bit.
a change on the USB data lines (dp/dm) occurs.
a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed).
a change on bvalid occurs (= VBUS threshold at 4.0 V is crossed).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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