LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 107

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
10.5.3 CCU1/2 branch clock configuration registers
Table 82.
Each generated output clock from the CCU has a configuration register. They all follow the
format as described in
On the LPC18xx, all branch clocks are in Run mode after reset. Auto and wake-up
features are disabled.
The clock can be configured to run in the following modes described by the bits RUN,
AUTO, and WAKEUP in the CLK_XXX_CFG registers:
RUN — The WAKEUP, PD, and AUTO control bits determine the activation of the branch
clock. If register bit AUTO is set the AHB disable protocol must complete before the clock
is switched off. The PD bit is set in
AUTO — Enable auto (AHB disable mechanism). The PMU initiates the AHB disable
protocol before switching the clock off. This protocol ensures that all AHB transactions
have been completed before turning the clock off.
WAKEUP — The branch clock is wake-up enabled when the PD bit in the Power Mode
register
These clocks will be switched on if a wake-up event is detected or if the PD bit is cleared.
If register bit AUTO is set, the AHB disable protocol must complete before the clock is
switched off.
Bit
0
1
2
3
4
5
6
7
31:8
(seeTable
Symbol
-
BASE_UART3_
CLK
BASE_UART2_
CLK
BASE_UART1_
CLK
BASE_UART0_
CLK
BASE_SSP1_
CLK
BASE_SSP0_
CLK
-
-
CCU2 base clock status register (CCU2_BASE_STAT, address 0x4005 2004) bit
description
All information provided in this document is subject to legal disclaimers.
80) is set and clocks which are wake-up enabled are switched off.
Rev. 00.13 — 20 July 2011
Table 83
Description
Reserved.
Base clock indicator for BASE_UART3_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_UART2_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_UART1_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_UART0_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_SSP1_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_SSP0_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Reserved.
Reserved.
and
Table
Table
Chapter 10: LPC18xx Clock Control Unit (CCU)
80.
85.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
-
1
1
1
1
1
1
-
-
107 of 1164
Access
-
R
R
R
R
R
R
-
-