LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 738

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.6.2.2 Synchronous master mode
32.6.3 RS-485/EIA-485 modes of operation
situation, the number of bits transmitted by the master and the number of bits transmitted
by the slave (received by the master) may not be aligned. It is assumed that a higher level
protocol ensures that complete characters are received when the master stops the clock.
Transmission of data during synchronous slave mode is most time-critical. First the
external serial input clock must be detected using edge detection logic. Then, data needs
to be shifted out and be stable before the sampling edge of the external serial clock.
Remark: In this mode the u_clk period is allowed to be 4x the serial clock period.
Synchronous master mode is enabled by setting the CSRC register bit to ‘1’. In this mode,
the external clock is generated internally by the baud-rate generation logic and is used to
clock the input and output serial data. The functionality of the baud-rate generation is
described in
The 1x baud rate clock is used to shift out the serial output data and to sample the serial
input data.
Synchronous master mode behaves similar to the slave mode, except that the serial input
data is not registered at the interface but is clocked in the UART clock domain at the
sampling edge of the serial clock.
During synchronous master mode, when start and stop bits are transmitted, the user can
enable the external clock continuously using cscen bit of the Synchronous Mode Control
register. This allows the connected slave to transmit data even when no data is
transmitted by the master itself.
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the UART to set the parity error and generate an interrupt.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored
and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it
will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The
processor can then read the address byte and decide whether or not to enable the
receiver to accept the following data.
While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be accepted
and stored in the RXFIFO regardless of whether they are data or address. When an
address character is received a parity error interrupt will be generated and the processor
can decide whether or not to disable the receiver.
Section
All information provided in this document is subject to legal disclaimers.
32.5.12.1. Auto-baud is not supported during synchronous mode.
Rev. 00.13 — 20 July 2011
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
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