LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 732

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.15 UART RS485 Control register
After reset the USART smart card interface will be disabled. After setting the SCIEN bit
the USART will be in ISO 7816-3 compliant asynchronous smart card mode T=0.
The NACKDIS bit is used to inhibit a nack response during T=0 (the I/O line is not pulled
low during the guard time to indicate an erroneous reception). The received character will
be stored in the RX FIFO but a parity error will be generated. It is up to the software to
handle the incorrect received character.
The PROTSEL bit is used to selected between the two supported smart card protocols
T=0 and T=1. More information on these protocols can be found in the ISO 7816-3
standard.
The retry bit field indicates the number of retransmission when receiving a NACK
response, which can be up to 7 trails. When the number is exceeded, an interrupt is
generated and the USART is locked until the FIFO is empty. This can be done by flushing
the FIFO. When no FIFO is available, or the FIFO is already empty, the interrupt can be
used by the software to determine the next action.
The guard time bit file is used to program the extra number of guard time cycles to allow
the smart card to process the information before sending a response. The extra guard
time can be programmed from 0 to 255, where 255 indicates the minimum possible
character length. This value is depending on the selected protocol and can be either 11
etu for protocol T=1 or 12 etu for protocol T=0.
Waiting times as defined in the standard cannot be programmed directly, but are
implemented using the CAP1 and CAP2 inputs of the timers. Use the CREG6 register in
the CREG block (see
polling signals.
Remark: The SCICTRL register should not be modified while sending or receiving data,
or data may be lost or corrupted.
Remark: The SCICTRL register should not be enabled in combination with the
SYNCCTRL register, as only asynchronous smart card is supported.
The RS485CTRL register controls the configuration of the UART in RS-485/EIA-485
mode.
Table 682. UART RS485 Control register (RS485CTRL - addresses 0x4008 104C (UART0),
Bit
0
Symbol
NMMEN
0x400C 104C (UART2), 0x400C 204C (UART3)) bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
Table
Rev. 00.13 — 20 July 2011
37) to set up the timers for polling the tx_active and rx_active
Description
NMM enable.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is disabled.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is enabled. In this mode, an address is detected
when a received byte causes the UART to set the
parity error and generate an interrupt.
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
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