LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 273

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
16.6.12 DMA Software Last Single Request Register
16.6.13 DMA Configuration Register
Table 207. DMA Software Last Burst Request Register (SOFTLBREQ, address 0x4000 2028)
The SOFTLSREQ Register is read/write and enables DMA last single requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Reading the register indicates which sources are requesting last single DMA
transfers. A request can be generated from either a peripheral or the software request
register.
Table 208. DMA Software Last Single Request Register (SOFTLSREQ, address 0x4000 202C)
The CONFIG Register is read/write and configures the operation of the DMA Controller.
The endianness of the AHB master interface can be altered by writing to the M bit of this
register. The AHB master interface is set to little-endian mode on reset.
Table 209. DMA Configuration Register (CONFIG, address 0x4000 2030) bit description
Bit
15:0
31:16
Bit
15:0
31:16
Bit
0
1
Symbol Value
E
M0
Symbol
SOFTLBREQ Software last burst request flags for each of 16
-
Symbol
SOFTLSREQ Software last single transfer request flags for each of
-
bit description
bit description
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Description
possible sources. Each bit represents one DMA
request line or peripheral function:
0 - writing 0 has no effect.
1 - writing 1 generates a DMA last burst request for the
corresponding request line.
Reserved. Read undefined. Write reserved bits as
zero.
Description
16 possible sources. Each bit represents one DMA
request line or peripheral function:
0 - writing 0 has no effect.
1 - writing 1 generates a DMA last single transfer
request for the corresponding request line.
Reserved. Read undefined. Write reserved bits as
zero.
Description
DMA Controller enable:
Disabled (default). Disabling the DMA Controller
reduces power consumption.
Enabled
AHB Master 0 endianness configuration:
Little-endian mode (default).
Big-endian mode.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
0x00
Reset
value
0x00
-
Reset
value
0x00
-
273 of 1164
Access
R/W
R/W
Access
R/W
-
Access
R/W
-