LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 114

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 90.
<Document ID>
User manual
Priority Reset input
1
2
3
4
External reset pin,
BOD, WWDT
CORE_RST
PERIPH_RST
MASTER_RST
Reset priority
11.3.1 Reset hierarchy
The hierarchy is as follows (see
1. External reset, BOD reset signal, WWDT time-out, and reset signal from the PMU
2. CORE_RST (inputs are the external reset pin, BOD reset, and the WWDT time-out
3. PERIPH_RST (input is the CORE_RST); resets all APB peripherals and the ARM
4. MASTER_RST (input is the PERIPH_RST); resets the ARM Cortex-M3 core and the
Fig 22. RGU Reset structure
•
•
BOD reset signal
WWDT time-out signal
reset); resets the whole chip including the WWDT and the configuration register block
CREG.
core, but not the WWDT and the CREG block.
AHB peripherals (DMA, USB0/1, LCD, SDIO, EMC, AES).
WWDT CREG/
yes
yes
no
no
RTC/
Event
router
yes
yes
no
no
All information provided in this document is subject to legal disclaimers.
master_rst_an(3)
periph_rst_an(2)
wwdt_rst_an(5)
core_rst_an(1)
bod_rst_an(4)
Rev. 00.13 — 20 July 2011
ext_rst_an(0)
pmc_rst_an
ABP
peripherals
yes
yes
yes
no
TRSTn
Table
Chapter 11: LPC18xx Reset Generation Unit (RGU)
Cortex-
M3 Core
yes
yes
yes
yes
delay=1
delay=1
delay=1
delay=3
delay=0
delay=3
delay=0
no sw
no sw
90):
AHB
peripherals
yes
yes
yes
yes
master_rst_out_n
periph_rst_out_n
m3,usb,lcd,etc...
wwdt_rst_out_n
core_rst_out_n
creg_rst_out_n
spi,etc ....
RGU EMC GPIO SRAM
yes
yes
yes
yes
yes
yes
yes
yes
TRSTn_loc
UM10430
© NXP B.V. 2011. All rights reserved.
yes
yes
yes
yes
controllers
yes
yes
yes
yes
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