LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1105

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.10.7.2.4 Test modes
The Disable Automatic Retransmission mode is enabled by programming bit DAR in the
CAN Control Register to one. In this operation mode the programmer has to consider the
different behavior of bits TXRQST and NEWDAT in the Control Registers of the Message
Buffers:
The Test mode is entered by setting bit TEST in the CAN Control Register to one. In Test
mode the bits TX1, TX0, LBACK, SILENT, and BASIC in the Test Register are writable. Bit
RX monitors the state of pins RD0,1 and therefore is only readable. All Test register
functions are disabled when bit TEST is reset to zero.
Silent mode:
bit SILENT to one.
In Silent Mode, the CAN controller is able to receive valid data frames and valid remote
frames, but it sends only recessive bits on the CAN bus, and it cannot start a
transmission. If the CAN Core is required to send a dominant bit (ACK bit, overload flag,
active error flag), the bit is rerouted internally so that the CAN Core monitors this dominant
bit, although the CAN bus may remain in recessive state. The Silent mode can be used to
analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits
(Acknowledge Bits, Error Frames).
Loop-back mode:
Test Register bit LBACK to one. In Loop-back Mode, the CAN Core treats its own
transmitted messages as received messages and stores them (if they pass acceptance
filtering) into a Receive Buffer.
This mode is provided for self-test functions. To be independent from external stimulation,
the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot
of a data/remote frame) in Loop-back mode. In this mode the CAN core performs an
internal feedback from its CAN_TXD output to its CAN_RXD input. The actual value of the
CAN_RXD input pin is disregarded by the CAN Core. The transmitted messages can be
monitored at the CAN_TXD pin.
Fig 172. CAN core in Silent mode
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When a transmission starts, bit TXRQST of the respective Message Buffer is reset
while bit NEWDAT remains set.
When the transmission completed successfully, bit NEWDAT is reset.
When a transmission failed (lost arbitration or error), bit NEWDAT remains set. To
restart the transmission, the CPU has to set TXRQST back to one.
The CAN core can be set in Silent mode by programming the Test register
All information provided in this document is subject to legal disclaimers.
The CAN Core can be set in Loop-back mode by programming the
Rev. 00.13 — 20 July 2011
C_CAN
TD0, TD1 RD0, RD1
= 1
Rx
CAN CORE
Tx
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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