LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 61

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
7.4.9 Part ID register
Table 37.
Table 38.
Bit
11:
5
12
13
14
15
16
31:
17
Bit
31:0
Symbol
-
I2S0_TX_SCK_IN_
SEL
I2S0_RX_SCK_IN_
SEL
I2S1_TX_SCK_IN_
SEL
I2S1_RX_SCK_IN_
SEL
EMC_CLK_SEL
-
Symbol
ID
CREG6 control register (CREG6, address 0x4004 312C) bit description
Part ID register (CHIPID, address 0x4004 3200) bit description
All information provided in this document is subject to legal disclaimers.
Description
<tbd>
Rev. 00.13 — 20 July 2011
Value Description
0
1
0
1
0
1
0
1
0
1
Reserved.
I2S0_TX_SCK input select
I2 S clock selected as defined by the I2S
transmit mode register
Audio PLL for I2S transmit clock MCLK input
and MCLK output. The I2S must be
configured in slave mode.
I2S0_RX_SCK input select
I2 S clock selected as defined by the I2S
receive mode register
Audio PLL for I2S receive clock MCLK input
and MCLK output. The I2S must be
configured in slave mode.
I2S1_TX_SCK input select
I2 S clock selected as defined by the I2S
transmit mode register
Audio PLL for I2S transmit clock MCLK input
and MCLK output. The I2S must be
configured in slave mode.
I2S1_RX_SCK input select
I2 S clock selected as defined by the I2S
receive mode register
Audio PLL for I2S receive clock MCLK input
and MCLK output. The I2S must be
configured in slave mode.
EMC_CLK divided clock select (see
Section
EMC_CLK_DIV not divided.
EMC_CLK_DIV divided by 2.
Reserved.
Chapter 7: LPC18xx Configuration Registers (CREG)
19.1).
Table
Table
Table
Table
745.
745.
744.
744.
UM10430
Reset
value
© NXP B.V. 2011. All rights reserved.
Reset
value
-
0
0
0
0
0
-
Access
…continued
61 of 1164
Access
-
R/W
R/W
R/W
R/W
R/W
-