LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 872

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
37.10 Details of I
<Document ID>
User manual
37.9.10 Status decoder and status register
37.9.8 Timing and control
37.9.9 Control register, CONSET and CONCLR
via the I
for details. The output clock pulses have a duty cycle as programmed unless the bus is
synchronizing with other SCL clock sources as described above.
The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for DAT, enables the comparator,
generates and detects START and STOP conditions, receives and transmits acknowledge
bits, controls the master and slave modes, contains interrupt request logic, and monitors
the I
The I
and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
The contents of the I
set bits in the I
writing to CONCLR will clear bits in the I
value written.
The status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I
generate vector addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26 possible bus states if all
four modes of the I
significant bits of the status register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The three least significant bits
of the status register are always zero. If the status code is used as a vector to service
routines, then the routines are displaced by eight address locations. Eight bytes of code is
sufficient for most of the service routines (see the software example in this section).
The four operating modes are:
Data transfers in each mode of operation are shown in
Figure
figures when describing the I
•
•
•
•
2
C operating modes
Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter
2
2
C-bus status.
C control register contains bits used to control the following I
142,
2
C Clock Control Registers. See the description of the SCLL and SCLH registers
Figure
2
C control register that correspond to ones in the value written. Conversely,
All information provided in this document is subject to legal disclaimers.
2
143, and
C block are used. The 5-bit status code is latched into the five most
2
C control register may be read as CONSET. Writing to CONSET will
Rev. 00.13 — 20 July 2011
Figure
2
C operating modes.
144.
2
C-bus status. The 5-bit code may be used to
2
Table 816
C control register that correspond to ones in the
Chapter 37: LPC18xx I2C-bus interface
lists abbreviations used in these
Figure
140,
2
C block functions: start
Figure
UM10430
© NXP B.V. 2011. All rights reserved.
141,
872 of 1164