LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 22

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

3.1 How to read this chapter
3.2 Features
3.3 Functional description
<Document ID>
User manual
This chapter applies to flashless parts LPC1850/30/20/10 only.
The boot ROM memory includes the following features:
AES capable parts also support:
The internal ROM memory is used to store the boot code. After a reset, the ARM
processor will start its code execution from this memory.
The ARM core is configured to start executing code, upon reset, with the program counter
being set to the value 0x0000 0000. The LPC18xx contains a shadow pointer that allows
areas of memory to be mapped to address 0x0000 0000. The default value of the shadow
pointer is 0x1040 0000, ensuring that the code contained in the boot ROM is executed at
reset.
Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If
the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is
determined by the states of the boot pins p2_8, P2_8, P1_2, and P1_1.
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UM10430
Chapter 3: LPC18xx Boot ROM
Rev. 00.13 — 20 July 2011
ROM memory size is 64 kB.
Supports booting from UART interfaces and external static memory such as NOR
flash, SPI flash, quad SPI flash.
Includes APIs for power control and OTP programming.
Includes SPIFI and USB drivers.
ISP mode for loading data to on-chip SRAM and execute code from on-chip SRAM.
CMAC authentication on the boot image.
Secure booting from an encrypted image.
Supports development mode for booting from a plain text image. Development mode
is terminated by programming the AES key.
API for AES programming.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
User manual
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