LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 961

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.2.6.2 Edge configuration register
Table 905. Level configuration register (HILO - address 0x4004 4000) bit description
This register works in combination with the level configuration register HILO (see
Table
The EDGE configuration register determines whether the event router responds to a level
change (EDGEn=1), or a constant level (EDGEn=0). The HILOn bit determines a
response to a rising edge (HILOn=1) or a falling edge (HILOn=0).
Table 906. EDGE and HILO combined register settings
When a HIGH level detect is active, the event router status bits cannot be cleared until the
signal is LOW. When a rising edge detect is active, the event router status bit can be
cleared right after the event has occurred.
Table 907. Edge configuration register (EDGE - address 0x4004 4004) bit description
Bit
15
16
18:17 -
19
31:20 -
HILOn
0
0
1
1
Bit
0
905) to configure the level or edge detection for each input to the event router.
Symbol
QEI_L
TIM14_L
RESET_L
Symbol
WAKEUP0_E
All information provided in this document is subject to legal disclaimers.
EDGEn
0
1
0
1
Value Description
0
1
0
1
-
0
1
-
Value Description
0
1
Rev. 00.13 — 20 July 2011
Level detect mode for QEI event.
Detect LOW level if bit 15 in the EDGE register is 0. Detect
falling edge if bit 15 in the EDGE register is 1.
Detect HIGH level if bit 15 in the EDGE register is 0.
Detect rising edge if bit 15 in the EDGE register is 1.
Level detect mode for combined timer output 14 event.
Detect LOW level if bit 16 in the EDGE register is 0. Detect
falling edge if bit 16 in the EDGE register is 1.
Detect HIGH level if bit 16 in the EDGE register is 0.
Detect rising edge if bit 16 in the EDGE register is 1.
Reserved.
Level detect mode for RESET event.
Detect LOW level if bit 17 in the EDGE register is 0. Detect
falling edge if bit 17 in the EDGE register is 1.
Detect HIGH level if bit 17 in the EDGE register is 0.
Detect rising edge if bit 17 in the EDGE register is 1.
Reserved.
Edge detect mode for WAKEUP0 event.
Level detect.
Edge detect. Detect falling edge if bit 0 in the HILO
register is 0. Detect rising edge if bit 0 in the HILO
register is 1.
Description
Detect LOW level
Detect falling edge
Detect HIGH level
Detect rising edge
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
Reset
value
0