LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 278

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 214. DMA Channel Control registers (CCONTROL, 0x4000 210C (C0CONTROL) to 0x4000 21EC (C7CONTROL))
<Document ID>
User manual
Bit
24
25
26
27
28
29
30
31
16.6.19.1 Protection and access information
bit description
Symbol
S
D
SI
DI
PROT1
PROT2
PROT3
I
16.6.20 Channel Configuration registers
AHB access information is provided to the source and destination peripherals when a
transfer occurs. The transfer information is provided by programming the DMA channel
(the Prot bits of the CCONTROL Register, and the Lock bit of the CCONFIG Register).
These bits are programmed by software. Peripherals can use this information if
necessary.
The eight CCONFIG Registers (C0CONFIG to C7CONFIG) are read/write with the
exception of bit[17] which is read-only. Used these to configure the DMA channel. The
registers are not updated when a new LLI is requested.
…continued
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Source AHB master select:
AHB Master 0 selected for source transfer.
AHB Master 1 selected for source transfer.
Destination AHB master select:
Remark: Only Master1 can access a peripheral. Master0 can
only access memory.
AHB Master 0 selected for destination transfer.
AHB Master 1 selected for destination transfer.
Source increment:
The source address is not incremented after each transfer.
The source address is incremented after each transfer.
Destination increment:
The destination address is not incremented after each transfer.
The destination address is incremented after each transfer.
Indicates that the access is in user mode or privileged mode:
Access is in user mode
Access is in privileged mode.
Indicates that the access is bufferable or not bufferable:
Access is not bufferable.
Access is bufferable.
Indicates that the access is cacheable or not cacheable:
Access is not cacheable.
Access is cacheable.
Terminal count interrupt enable bit.
The terminal count interrupt is disabled.
The terminal count interrupt is enabled.
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
278 of 1164
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W