LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 397

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 338. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to
20.7 Functional description
<Document ID>
User manual
Bit
21
22
23
31:24 -
Symbol
TXI
TXR
TXE
0x4000 61D4 (ENDPTCTRL5)) bit description
20.7.1 OTG core
20.7.2 Host data structures
20.7.3 Host operational model
20.7.4 ATX_RGEN module
Value
0
1
0
1
-
The OTG core forms the main digital part of the USB-OTG. See the USB EHCI
specification for details about this core.
See Chapter 4 of Enhanced Host Controller Interface Specification for Universal Serial
Bus 1.0.
See Chapter 3 of Enhanced Host Controller Interface Specification for Universal Serial
Bus 1.0.
There are a number of requirements for the reset signal towards the ATX transceiver,
these are as follows:
•
•
•
it requires the clocks to be running for a reset to occur correctly.
it must see a rising edge of reset to correctly reset the clock generation module.
the reset must be a minimum of 133 ns (4  30 MHz clock cycles) in duration to reset
all logic correctly.
Description
Tx data toggle inhibit
This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data
toggle sequence and always accept data packets regardless of their
data PID.
Enabled
Disabled
Tx data toggle reset
Write 1 to reset the PID sequence.
Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data
PID’s between the host and device.
Tx endpoint enable
Remark: An endpoint should be enabled only after it has been
configured
Endpoint disabled.
Endpoint enabled.
reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
…continued
Reset
value
0
1
0
0
UM10430
© NXP B.V. 2011. All rights reserved.
Access
R/W
WS
R/W
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