LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 576

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LPC1837FET256,551

Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr

Specifications of LPC1837FET256,551

Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
 Details
Other names
935293795551
NXP Semiconductors
Table 491. Buffer to pixel mapping for 64 x 64 pixel cursor format
<Document ID>
User manual
Data bits
5:4
3:2
1:0
(1, 0)
(2, 0)
(3, 0)
23.7.6 Gray scaler
23.7.7 Upper and lower panel formatters
0
(17, 0)
(18, 0)
(19, 0)
Cursor pixel encoding
Each pixel of the cursor requires two bits of information. These are interpreted as Color0,
Color1, Transparent, and Transparent inverted.
In the coding scheme, bit 1 selects between color and transparent (AND mask) and bit 0
selects variant (XOR mask).
Table 492
Table 492. Pixel encoding
A patented gray scale algorithm drives monochrome and color STN panels. This provides
15 gray scales for monochrome displays. For STN color displays, the three color
components (RGB) are gray scaled simultaneously. This results in 3375 (15x15x15)
colors being available. The gray scaler transforms each 4-bit gray value into a sequence
of activity-per-pixel over several frames, relying to some degree on the display
characteristics, to give the representation of gray scales and color.
Formatters are used in STN mode to convert the gray scaler output to a parallel format as
required by the display. For monochrome displays, this is either 4 or 8 bits wide, and for
color displays, it is 8 bits wide.
worth of data in a repeating sequence.
Value
00
01
10
11
4
(33, 0)
(34, 0)
(35, 0)
shows the pixel encoding bit assignments.
Description
Color0.
The cursor color is displayed according to the Red-Green-Blue (RGB) value
programmed into the CRSR_PAL0 register.
Color1.
The cursor color is displayed according to the RGB value programmed into the
CRSR_PAL1 register.
Transparent.
The cursor pixel is transparent, so is displayed unchanged. This enables the visible
cursor to assume shapes that are not square.
Transparent inverted.
The cursor pixel assumes the complementary color of the frame pixel that is displayed.
This can be used to ensure that the cursor is visible regardless of the color of the
frame buffer image.
8
All information provided in this document is subject to legal disclaimers.
(49, 0)
(50, 0)
(51, 0)
12
Rev. 00.13 — 20 July 2011
Offset into cursor memory
(16 * y)
Table 493
(1, y)
(2, y)
(3, y)
(16 * y) +4
shows a color display driven with 2 2/3 pixels
(17, y)
(18, y)
(19, y)
(16 * y) + 8
(33, y)
(34, y)
(35, y)
Chapter 23: LPC18xx LCD
(16 * y) + 12
(49, y)
(50, y)
(51, y)
UM10430
© NXP B.V. 2011. All rights reserved.
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