LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 863

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.7.7.1 Interrupt in Monitor mode
37.7.7.2 Loss of arbitration in Monitor mode
37.7.8 I
[1]
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).
Subsequent to an address-match detection, interrupts will be generated after each data
byte is received for a slave-write transfer, or after each byte that the module “thinks” it has
transmitted for a slave-read transfer. In this second case, the data register will actually
contain data transmitted by some other slave on the bus which was actually addressed by
the master.
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.
In monitor mode, the I
the bus master or issue an ACK). Some other slave on the bus will respond instead. This
will most probably result in a lost-arbitration state as far as our module is concerned.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected.
These registers are readable and writable and are only used when an I
to slave mode. In master mode, this register has no effect. The LSB of ADR is the General
Call bit. When this bit is set, the General Call address (0x00) is recognized.
If these registers contain 0x00, the I
four registers (including ADR0, see
reset.
Table 811. I
Bit
0
7:1
31:8
2
C Slave Address registers
When the ENA_SCL bit is cleared and the I
time becomes important. To give the part more time to respond to an I
DATA _BUFFER register is used
time.
Symbol
GC
Address
-
(ADR3) (I2C0) and 0x400E 0020 (ADR1) to 0x400E 0028 (ADR3) (I2C1)) bit
description
2
C Slave Address registers (ADR - address 0x400A 1020 (ADR1) to 0x400A 1028
All information provided in this document is subject to legal disclaimers.
Description
General Call enable bit.
The I
Reserved. The value read from a reserved bit is not defined.
2
2
Rev. 00.13 — 20 July 2011
C module will not be able to respond to a request for information by
C device address for slave mode.
(Section
Table
2
C will not acknowledge any address on the bus. All
37.7.9) to hold received data for a full 9-bit word transmission
2
C no longer has the ability to stall the bus, interrupt response
805) will be cleared to this disabled state on
Chapter 37: LPC18xx I2C-bus interface
2
C interrupt under these conditions, a
UM10430
2
© NXP B.V. 2011. All rights reserved.
C interface is set
Reset value
0
0x00
-
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