LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 626

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
25.7.5 Timer prescale counter registers
25.7.6 Timer match control registers
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship of the resolution of the
timer versus the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale register,
the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.
This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 PCLKs
when PR = 1, etc.
Table 538. Timer prescale counter registers PC(PC - addresses 0x4008 4010 (TIMER0),
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Table 539. Timer match control registers MCR (MCR - addresses 0x4008 4014 (TIMER0),
Bit
31:0
Bit
0
1
2
3
4
5
Table
Symbol Value Description
MR0I
MR0R
MR0S
MR1I
MR1R
MR1S
539.
Symbol
PC
0x4008 5010 (TIMER1), 0x400C 3010 (TIMER2), 0x400C 4010 (TIMER3)) bit
description
0x4008 5014 (TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014 (TIMER3)) bit
description
All information provided in this document is subject to legal disclaimers.
1
0
1
0
1
1
0
1
0
1
0
1
0
Rev. 00.13 — 20 July 2011
Interrupt on MR0
Interrupt is generated when MR0 matches the value in the TC.
Interrupt is disabled
Reset on MR0
TC will be reset if MR0 matches it.
Feature disabled.
Stop on MR0
TC and PC will be stopped and TCR[0] will be set to 0 if MR0
matches the TC.
Feature disabled.
Interrupt on MR1
Interrupt is generated when MR1 matches the value in the TC.
Interrupt is disabled.
Reset on MR1
TC will be reset if MR1 matches it.
Feature disabled.
Stop on MR1
TC and PC will be stopped and TCR[0] will be set to 0 if MR1
matches the TC.
Feature disabled.
Description
Prescale counter value.
Chapter 25: LPC18xx Timer0/1/2/3
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
Reset
value
0
0
0
0
0
0