LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 406

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 37. Endpoint queue head organization
ENDPOINTLISTADDR
20.9.1.1 Endpoint capabilities and characteristics
20.9.1 Endpoint queue head (dQH)
Device queue heads are arranged in an array in a continuous area of memory pointed to
by the ENDPOINTLISTADDR pointer. The even –numbered device queue heads in the list
support receive endpoints (OUT/SETUP) and the odd-numbered queue heads in the list
are used for transmit endpoints (IN/INTERRUPT). The device controller will index into this
array based upon the endpoint number received from the USB bus. All information
necessary to respond to transactions for all primed transfers is contained in this list so the
Device Controller can readily respond to incoming requests without having to traverse a
linked list.
Remark: The Endpoint Queue Head List must be aligned to a 2k boundary.
The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is
a 48-byte data structure, but must be aligned on 64-byte boundaries. During priming of an
endpoint, the dTD (device transfer descriptor) is copied into the overlay area of the dQH,
which starts at the nextTD pointer DWord and continues through the end of the buffer
pointers DWords. After a transfer is complete, the dTD status DWord is updated in the
dTD pointed to by the currentTD pointer. While a packet is in progress, the overlay area of
the dQH is used as a staging area for the dTD so that the Device Controller can access
needed information with little minimal latency.
This DWord specifies static information about the endpoint, in other words, this
information does not change over the lifetime of the endpoint. Device Controller software
should not attempt to modify this information while the corresponding endpoint is enabled.
Endpoint Queue Heads
Endpoint dQH0 - Out
Endpoint dQH5 - Out
Endpoint dQH1 - Out
Endpoint dQH5 - In
Endpoint dQH0 - In
All information provided in this document is subject to legal disclaimers.
dQH
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Endpoint Transfer
Descriptors dTD
transfer buffer
dTD
dTD
dTD
pointer
transfer buffer
pointer
transfer buffer
TRANSFER
pointer
BUFFER
dTD
TRANSFER
BUFFER
TRANSFER
BUFFER
transfer buffer
pointer
TRANSFER
UM10430
BUFFER
© NXP B.V. 2011. All rights reserved.
406 of 1164