LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 717

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.5 UART Interrupt Identification Register
Table 668. UART Interrupt Enable Register when DLAB = 0 (IER - addresses 0x4008 1004
IIR provides a status code that denotes the priority and source of a pending interrupt. The
interrupts are frozen during a IIR access. If an interrupt occurs during a IIR access, the
interrupt is recorded for the next IIR access.
Table 669. UART Interrupt Identification Register, read only (IIR - addresses 0x4008 1008
Bits IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
Bit
9
31:10 -
Bit
0
3:1
5:4
7:6
8
9
31:10 -
Symbol
ABTOINTEN
Symbol
INTSTATUS
INTID
-
FIFOENABLE
ABEOINT
ABTOINT
(UART0), 0x400C 1004 (UART2), 0x400C 2004 (UART3) ) bit description
(UART0), 0x400C 1008 (UART2), 0x400C 2008 (UART3)) bit description
All information provided in this document is subject to legal disclaimers.
Value
Value Description
Rev. 00.13 — 20 July 2011
0x3
0x2
0x6
0x1
0x0
0
1
0
1
Enables the auto-baud time-out interrupt.
Disable auto-baud time-out Interrupt.
Enable auto-baud time-out Interrupt.
bits. The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved
Interrupt status.
Note that IIR[0] is active low. The pending interrupt can be
determined by evaluating IIR[3:1].
At least one interrupt is pending.
No interrupt is pending.
Interrupt identification.
IER[3:1] identifies an interrupt corresponding to the UART
Rx FIFO. All other combinations of IER[3:1] not listed
below are reserved (100,101,111).
Priority 1 (highest) - Receive Line Status (RLS).
Priority 2 - Receive Data Available (RDA).
Priority 2 - Character Time-out Indicator (CTI).
Priority 3 - THRE Interrupt.
Priority 4 (lowest) - Reserved.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Copies of FCR[0].
End of auto-baud interrupt.
True if auto-baud has finished successfully and interrupt is
enabled.
Auto-baud time-out interrupt.
True if auto-baud has timed out and interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
…continued
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Reset
value
0
NA
Reset
value
1
0
NA
0
0
0
NA